Hardware Accelerator for Sign Language Detection on FPGA

Abstract: This project aims to develop a hardware accelerator for real-time sign language detection using Atlera DE10- Lite FPGA board. Sign language recognition is essential for bridging communication gaps between sign language users and the broader population. By leveraging the parallel processing capabilities and energy efficiency of FPGAs, the system ensures low latency and high accuracy in gesture recognition. The approach involves designing an optimized Convolutional Neural Network (CNN) architecture tailored for FPGA implementation and incorporating preprocessing techniques to enhance robustness against environmental variability.

Keywords: Hardware Accelerator, Convolutional Neural Network, Sign language detection, Altera DE10-Lite FPGA.