Design and Comparative Analysis of 6T CMOS SRAM Cell Across Various Technology Nodes

Abstract: This paper presents a comprehensive design and comparative performance analysis of a conventional 6- transistor (6T) CMOS static random-access memory (SRAM) cell implemented across four advanced CMOS technology nodes: 120 nm, 90 nm, 70 nm, and 50 nm. The SRAM cell architecture comprises two cross-coupled inverters and two access transistors, designed under identical specifications to systematically isolate the effects of technology scaling. Layout design and transient circuit simulations were conducted using Microwind VLSI design tool with BSIM4 transistor models to characterise cell behaviour during read and write operations. BSIM4 models enable accurate representation of device-level effects including leakage current and short-channel phenomena, which become increasingly prominent in scaled technologies. The analysis focuses on two critical performance metrics: dynamic power consumption and physical layout area. Results demonstrate that both power dissipation and silicon area decrease monotonically with technology node reduction. Specifically, the 50 nm implementation achieves the lowest power consumption and most compact layout, while the 120 nm node exhibits comparatively higher values. These findings elucidate the impact of technology scaling on fundamental SRAM characteristics and provide quantitative insights to inform efficient memory design and optimization in modern VLSI and system-on-chip implementations.

Keywords: 6T SRAM, CMOS Technology, Microwind, Power Consumption, Cell Area, Technology Scaling, VLSI Design, Nano Technology Nodes, Memory Management.