VERY LOW COMPLEXITY LOW LATENCY ARCHITECTURE FOR DATA ENCODING HARD SYNTHETIC ERROR CORRECTING CODE

Abstract: In current scenario, there are situations in a computing system where incoming information needs to be compared with a piece of stored data to locate the matching entry, e.g., cache tag array lookup and translation look-aside buffer matching. Nowadays the reliability issues of memory are Event Upsets (EUs), which are able to invert the stored logical value in memory cells. This issue is more serious when the affected memory cells are part of the configuration memory used for programming the circuit functionality. The consequences may be alterations of the circuit functionality causing errors which may only be corrected by reprogramming the device. A new architecture for matching the data protected with an error-correcting code (ECC) is proposed in brief to reduce latency and complexity. The proposed architecture is based on the fact that the codeword of an ECC is usually represented in a systematic form consisting of the raw data and the parity information generated by encoding, and the proposed architecture parallelizes the comparison of the data and that of the parity information. To further reduce the latency and complexity, in addition, a new butterfly-formed weight accumulator (BWA) is proposed for the efficient computation of the Hamming distance. Grounded on the BWA, the proposed architecture examines whether the incoming data matches the stored data, and if not it aims to locate the erroneous bit and they are corrected. The empirical evaluation proves that the proposed methodology discovers the best service for reliability issues of memory.

Keywords: Butterfly-Formed Weight Accumulator, Translation Look-Aside Buffer, ECC, EDC, Decimal Matrix Code.