Simulation of Graded Channel Double Gate Junctionless Transistor for Low Power and High Performance

Abstract: This paper proposes a novel structure of n-MOS Graded Channel Double Gate Junctionless transistor (GC DG JLT). Using TCAD the design and characteristics of GC DG JLT are compared with SC DG transistor with equal dimensions. From the results, it is observed that as the side gate voltage of GC DG JLT is increased, the surface potential also increases which ultimately increases the current driving capability. SC DG transistor has a prominent hot electron effect compared to GC DG JLT as the electric field distribution is more than 50% at drain side in SC DG transistor. It has been also observed that on- state current of GC DG JLT is more than that of the SC DG transistor. Threshold voltage roll-off is also less in GC DG JLT when the side gate length is varied. For the 20 nm main channel length, the DIBL is improved by 33% for the GC DG JLT compared to SC DG transistor. The Transconductance of the GC DG JLT is three times more than that of SC DG transistor at a gate voltage of 0.6V. The Sub-threshold slope of GC DG JLT is improved to 53% compared to SC DG transistor when the side gate length is length is 30nm and main gate length is 20 nm. Gm/IDS is the minimum in the saturation region which mean that drain to source current is most in the saturation region for the GC DG JLT.

Keywords: Graded channel DG JLT (GC DG JLT), Shielded channel DG transistor (SC DG), Drain induced barrier lowering (DIBL), Transconductance (Gm), Short channel effects (SCE), Sub- threshold Slope (SS)