Performance Analysis of RHBD 14T and 15T SRAM Cells Using Dual Rail Voltage Technique

Abstract: Solar particles events (SPE) generate high radiation in memory devices if they are exposed to solar radiation for long hours. Especially in SRAM units, the occurrence of Single Event Upsets (SEU) fluctuates the magnitude of voltages. The severity of SEU leads to a change in the output bit of memory devices. Therefore, a dynamic fault management system with voltage protection is necessary with a self-adaptive multiprocessing platform.In this paper, a dual-rail voltage (DRV) scheme was applied on 14T SRAM devices, 15T SRAM devices, Modified 14T SRAM devices, and Modified 15T SRAM circuits. Here 22nm and 16nm technology-based FinFET, CNTFET, GNRFET along with transistors based on widths of the devices during pullup and pulldown modes are tested and performances are compared using read static noise margin (RSNM) and write static noise margin (WSNM). Circuits are implemented using Tanner 16.5 version. Using MATLAB, performance metrics like SNM, read delay and write delay are plotted. The DRV scheme minimizes the voltage utility rate and self-error correction was enhanced by replacing the PMOS units with NMOS on controlling mode. The optimized 16nm FinFET is 32.6% effective in terms of power and 17.9% effective in terms of delay. SRAM cells were demonstrated which minimized latency and low voltage operation with fault protect.

Keywords: SRAM, RHBD, space applications, radiation hardness, SEU.