DESIGN AND TEST OF EMBEDDED BIST ARCHITECTURE

Abstract: Input vector monitoring concurrent BIST schemes are the class of online BIST techniques that overcomes the problems appearing separately in online and in offline BIST in a very effective way. This paper briefly presents an input vector monitoring concurrent BIST scheme, which monitors a set of vectors called window of vectors reaching the circuit inputs during normal operation, and the use of a CAM memory cell to store the relative locations of the vectors. The proposed scheme is evaluated based on the hardware overhead and the concurrent test latency (CTL) (i.e.)during the normal operation of the circuit, the time required to complete the testing operation; which shows to perform significantly better than previously proposed schemes with respect to the hardware overhead and CTL tradeoff.

Keywords: Built-in-Self Test, concurrent testing, input vector monitoring.