ABSTRACT, CORRECT BY CONSTRUCTION AND FASTER REGISTER MODELING OF AMBA APB BUS

Abstract: The1SoC (System on Chip) uses1AMBA1APB as an on chip bus.APB1is1low1bandwidth1and low performance1bus used to1connect the1peripherals like UART, Keypad,1Timer and1other peripheral devices to the bus1architecture. This paper describes the1design generation1of AMBA1APB (Advanced Peripheral Bus) protocol using Perl scripting language.1Here1main aim is to reduce1human interface in design1part so we can reduce common syntax errors. Per1 generates the Verilog design code of APB1slave and its1corresponding test bench, where all its1specifications1are there in XML script. This code1is simulated in QuestaSim. Finally1wave forms and1code coverage1reports are analyzed.

Keywords: AMBA, APB, Perl, SoC, XML, XLS