OPTIMIZED AREA-DELAY AND POWER EFFICIENT CARRY SELECT ADDER

Abstract: In the design of Digital Integrated Circuits area occupancy, delay and power play an important role because of the increasing necessity of portable and fast systems. Adders are one of the most widely used digital components in various Digital Circuits. Carry Select Adder (CSLA) is one of the fastest adders used in many processors, multipliers, and different applications. Carry select method is having a good compromise between cost and performance in carry propagation method. In this paper a modified area and low power carry select adder along with lower delay is proposed. The proposed system has low area and power consumption with lower delay suitable for FPGA design than the existing carry select adders. Due to the optimized area, power and delay, the proposed CSLA design is a good substitution for all the existing CSLA. The proposed architecture is designed using VHDL and is then synthesized using XILINX 13.2i and is simulated in ISim for Spartan 3E FPGA.

Keywords: carry select adder, area efficient, delay efficient, low power adder