IMPLEMENTATION OF HIGH SPEED MULTIPLIER USING FAST PARALLEL PREFIX ADDER

Abstract: With the rapid advancement in information technology, there is a huge demand for high speed processors. This has led to design of advanced processors capable of performing all mathematical computations at a faster speed. Multiplication is one such dominating computational technique which plays an important role as far as speed is concerned. In this paper, design and implementation of multiplier using Vedic mathematics named as Urdhva Triyakbhyam which incorporates Kogge Stone adder is presented. Adder is a parallel prefix derived from carry look-ahead adder which is the faster. This multiplier is implemented on Xilinx Board is shown to have exhibited high performance in terms of speed in the simulations.

Keywords: Urdhva Triyakbhyam, Kogge Stone adder, Xilinx Board.