Abstract: A methodology for energy–delay optimisation of digital circuits is given. In this method is useful to minimize the delay of representative carry-look ahead adders underneath energy constraints. Impact of varied design choices, as well as the carry-look ahead tree arrangement and logic approach, are analyzed in the energy–delay area and verified through optimisation. The results of the optimisation is verified on a design of the fastest adder found, a 240-ps Ling sparse domino adder in one V, 90 nm CMOS. The optimality of the results is assessed against the impact of technology scaling. In this paper, we tend to inspire the conception of comparison very giant scale integration adders based on their energy-delay characteristics and present results of our estimation technique. This stems from a requirement to form appropriate selection at the beginning of the design methodology. The estimation is fast, not requiring extensive simulation or use of CAD tools, however sufficiently correct to provide guidance through numerous choices in the design method.
Keywords: Adders, digital arithmetic, digital circuits, Carry skip adder (CSKA), energy efficient, high performance, hybrid variable latency adders, voltage scaling.