**Abstract:**
In current scenario, the reversible logic design attracting more interest due to its low power consumption. Reversible logic is very important in low-power circuit design. The important reversible gates used for reversible logic synthesis are Feynman Gate, Fredkin gate, Toffoli gate etc. This paper present a basic reversible gate to build more complicated circuits which can be implemented in ALU, some sequential circuits as well as in some combinational circuits. It also gives brief idea to build adder circuits using the basic reversible gate like peres gate This paper proposes a novel 4x4 bit reversible fault tolerant multiplier circuit which can multiply two 4-bit numbers. This based on two concepts. The partial products can be generated in parallel using PG gates and thereafter the addition is done by using reversible parallel adder designed from PFAG gates. Thus, this paper provides idea for building of more complex system which can execute more complicated operations using reversible logic.

**Keywords:**
Garbage output, Peres gate, PFAG, Reversible logic