Abstract: Design of High Efficiency Carry Select Adder Using SQRT Technique presents many opportunities for increasing the speed and reducing the area of any data processor. Only Carry Select Adder (CSLA) is the fastest adders which are used in many data-processing processors to perform fast arithmetic operation. From the structure of the CSLA, it is clear that there is scope for reducing the area and delay in the CSLA. In this thesis, we have implemented a carry select adder for the computational process, these modules are programmed in VHDL Carry Select Adder (CSLA) is the fastest adder in all other adder. This work uses very simple and efficient gate-level modification to reduce the area and delay of the CSLA. Based on this modification 8-, 16-, 32-bit square-root CSLA (SQRT CSLA) architecture has been developed and it is compared with the regular SQRT CSLA architecture. The proposed design has reduced area and delay as compared with the regular SQRT CSLA with only a slight reducing the delay. This work evaluates the performance of the proposed designs in parameters that is delay, area, and their products with logical effort. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
Keywords: Carry Save Adder, Carry Select Adder, Ripple Carry Adder, and Binary to Excess-1 Converter, Square root CSA, and VHDL.