Abstract: The main objective of this paper is to design a area efficient and high speed floating-point (FP) butterfly architecture for a signal processing applications. The butterfly architectures used in Fast Fourier Transform (FFT) algorithms. Most of the butterfly architectures uses fixed point arithmetic than the FP arithmetic because of lesser speed but main advantage is the high dynamic range. The limitation of FP arithmetic is overcome by using a FDPA unit but it consume more area. This draw back overcome by using a Coordinate Rotation Digital Computer (CORDIC) algorithm. In this paper we propose a CORDIC Multiplier based redundant floating point butterfly architecture for a signal processing applications. The proposed work synthesis is carried out by using XILINX ISE synthesis tool on the XILINX 14.7 platform and simulated using Model Sim simulator. The performance of this design is evaluated on XILINX Spartan3 family device.
Keywords: CORDIC algorithm, FDPA unit, Floating-point, Fixed –point